ansys.net search results
quick file search:
    home » search results
 
 
Specific Search Results Below:
 
Optimizing Board-level Reliability of an Underfilled, Stacked Chip Scale Package
  Zane E. Johnson, Nathan R. Schneck
  "Previously benchmarked finite-element (FE) models of a stacked chip scale package (CSP) are used to identify optimum underfill material properties under drop-impact and accelerated temperature cycling (ATC) stress conditions. The simulation sets indicate that an underfill having a modulus of 26 GPa and CTE of 25 ppm/K maximizes drop life and does no harm to ATC performance for both Sn63Pb37 and SAC305 solder joints. The methodology described can be applied to other package styles, material sets, and stress conditions."
[permalink]
 
Average Rating: 10.0 (1 vote)  
Rate this item: